1. Field of the Invention
The invention concerns a semiconductor power component with two successive opposed polarity planar pn junctions which has positive tapers on its lateral surface in the vicinity of both pn junctions.
2. Description of the Prior Art
Semiconductor power elements with two successive opposed polarity pn junctions can, for example, be used as thyristors (cf. e.g. Kohl, ETZ-A 89 (1968) pp. 131-135: Ref. 1) where at least one more pn junction than mentioned is provided, or even as voltage limiters (cf. e.g. Lawatsch and Weisshaar, Brown Boveri Review, Sept. 1972, Vol. 59, pp. 476-482: Ref. 2). In practice the pn junctions are nearly always planar since non-planar pn junctions give rise to technological and even electrical difficulties.
By "positive taper" is meant a slope in the lateral surface of the semiconductor power element with respect to the plane of the pn junction such that the cross section of the element shrinks as the metallurgic pn transition is traversed in the direction of the more weakly doped of the two adjacent zones, or in other words, such that the cross section of the element in the more highly doped region is greater, and/or in the more weakly doped region less than that in the plane of the metallurgic pn transition (cf. e.g. Davies and Gentry, IEEE Trans. on El. Dev. Vol. ED-11, July 1964, pp. 313-323: Ref. 3; or Cornu, IEEE Trans. on El. Dev. Vol. ED-20, April 1973, pp. 347-352: Ref. 4). In the reverse case, one speaks of a "negative taper".
The terms "positive" and "negative" taper imply unsymmetrically doped pn-transitions, i.e., of a type of which a more highly doped region adjoins a more weakly doped one.
The purpose of the taper is to reduce the electric field strength at the lateral surface so that any breakdown occurs inside the semiconductor element and never out over the surface. Surface breakdown is much more difficult to control and readily leads to destruction of the element. With positive taper, angles of about 30.degree. (Ref. 1 p. 132, left column, second paragraph from the bottom) are sufficient to guarantee restriction of an avalanche breakdown to the interior. With negative tapers, however, angles less than 1.degree. are necessary to be able to withstand voltages of the order to 3.5 KV. This results in a very considerable loss in usable element surface and introduces cooling problems in addition to others, since the taper cannot practically be brought into contact with a heat sink.
Consequently various methods have already been disclosed for avoiding the aforementioned problems.
Thus, for example, Kohl (Solid-State Electronics 1968, Vol. II, pp. 501-502: Ref. 5) proposed a mesa-shaped lateral contour with double phase.
Oisuka (IEE Conf. Publ. No. 53, Part 1 (1969) pp. 32-38: Ref. 6) proposed putting a ring-shaped groove in the silicon wafer of the element which cuts the forward blocking pn transition in such a way that the cross sectional area decreases with passage through the pn transition into the more weakly doped region.
Lastly, Gerecke (e.g. DT-05 1,439,215 : Ref. 7), early in 1962, proposed a dovetailed shape for the semiconductor element.
Further attempts at solutions in this vein are known, e.g. in U.S. Pat. No. 3,575,644 (Ref. 8) and in DT-AS No. 1,251,440 (Ref. 9).
Thus far, however, none of the known solutions have been able to carry over into actual practice. The reason for this is probably that all known structures present great technological problems in manufacture and it was obviously not realized to what extent advantages were to be obtained by means of the structures. Such knowledge was lacking because the properties of the known structures important for a semiconductor power element have not thus far been understandable theoretically since the relationships in such structures can be described only by systems of complex differential equations not soluble in closed form (cf. e.g. Ref. 3 and 4).
The aim of the present invention is to select from the multiplicity of known structures, and point out the special properties of, those permitting the production of semiconductor power elements that withstand voltages even greater than 3500 volts, in which, therefore, avalanche breakdown occurs only above 3500 v.